Download PDF by Ashok B. Mehta: ASIC/SoC Functional Design Verification: A Comprehensive

By Ashok B. Mehta

This publication describes intimately all required applied sciences and methodologies had to create a entire, sensible layout verification procedure and setting to take on the hardest activity of ensuring first-pass operating silicon.  the writer first outlines the entire verification sub-fields at a excessive point, with simply enough intensity to permit an engineer to know the sector ahead of delving into its detail.  He then describes intimately common applied sciences resembling UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog useful Coverage), CDV (Coverage pushed Verification), Low strength Verification (Unified strength layout UPF), AMS (Analog combined sign) verification, digital Platform TLM2.0/ESL (Electronic approach point) method, Static Formal Verification, good judgment Equivalency fee (LEC), Acceleration, Emulation, Hardware/Software Co-verification, strength functionality zone (PPA) research on a digital platform, Reuse technique from Algorithm/ESL to RTL, and different total methodologies.

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ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies by Ashok B. Mehta


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