By Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul
This monograph relies at the 3rd author's lectures on computing device structure, given in the summertime semester 2013 at Saarland collage, Germany. It includes a gate point development of a multi-core computing device with pipelined MIPS processor cores and a sequentially constant shared memory.
The publication includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache dependent sequentially constant shared reminiscence. This opens find out how to the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and therefore deterministic. against this the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.
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Additional info for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Lecture Notes in Computer Science)
A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Lecture Notes in Computer Science) by Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul